Senior ASIC Designer (27238)

Are you a digital IC or ASIC designer? Are you bored of making the same old designs year after year? Are you looking for an exciting new challenge? Then this is the role for you.

This well-funded team develop ASICs that are integral to the dominant position they hold in the marketplace. Their products and technologies are used in the consumer electronics industry and provide the underpinnings for many end-user features. They are constantly looking to advance their portfolio adding new features to existing products and also creating new technologies to open up new markets. To this end they have an active R&D department and are one of the largest generators of patents in the UK.

As a senior engineer you will be involved in all aspects of ASIC design from writing IP design specifications through to benchtop validation testing of final silicon. This will involve writing RTL code in Verilog and SystemVerilog, using EDA software from Siemens and Synopsys, and developing custom testing code using TCL and Python.

Requirements:

• Extensive industrial experience of the full digital IC development process including specification, design, simulation, synthesis, verification, and validation
• Good knowledge of chip architecture design including clock and reset networks, power domain structures, and AMBA protocols
• Good knowledge of verification techniques including verification IP for real-world testing, assertion-based verification methods (SVA), and UVM
• Strong skills in Verilog and SystemVerilog

Having recently relocated to larger offices the team continues to grow fuelled by sales of their technologies around the world. While such growth can bring problems, they have been diligent in maintaining the friendly and ambitious work environment that has been so important to their success so far. They attract world leaders and run internal training to spread knowledge and encourage professional and personal growth for all employees. Alongside the competitive salary, on offer are tech-company style perks such as lunchtime leisure activities and free breakfasts and the more conventional 25 days holiday (plus bank holidays) and private health insurance.

Keywords: Verilog, SystemVerilog, RTL, Static Timing Analysis, STA, GDS Layout, Clock and Reset Network, Power Domain Structure, I2C, SPI, UART, SWD, JTAG, AMBA, AHB, APB, AXI, Test Insertion, MBIST, EDA, Questa, VCS, DesignCompiler, Spyglass, DFT, UVM, SVA, VIP, UPF, Bash, TCL, Python, Pytest, Jenkins, CI/CD, Xilinx, FPGA, Vivado, ChipScope, ARM Cortex-M

Please note: even if you don’t have exactly the background indicated, do contact us now if this type of job is of interest – we may well have similar opportunities that you would be suited to. And of course, we always get your permission before submitting your CV to a company.

Recommend for £250 – see www.ecmselection.co.uk/tell-a-friend for details.